שאלה | Which of the following scenarios best illustrates a hazard in CPU pipelining ?

Which of the following scenarios best illustrates a hazard in CPU pipelining ?

		The CPU clock speed is increased to allow instructions to move faster through the pipeline
		A set of instructions is being executed sequentially with no overlap in their execution stages
		An instruction in the pipeline requires data that is yet to be written back from a previous instruction, causing a delay in execution
		The pipeline is flushed and refilled with new instructions after a branch prediction failure
		Two instructions are being executed simultaneously with no dependency on each other